The present invention relates broadly to storage circuits, and in particular to an automatic data restore apparatus for a temporary store memory unit.
In the prior art metal nitride oxide semiconductor (MNOS) memories with short cycle times are being developed for application in various systems. One such type memory is known as a Temporary Store Memory (TSM) and is used as a RAM with write cycle times less than 2 microseconds. In such an application the MNOS transistors which generally comprise the nonvolatile storage are shifted in threshold over a region of a few volts and are never shifted to the full extent (saturated)) either most positive or most negative due to the short write pulses that are involved. Saturation of the memory transistors is prevented so that subsequent write cycles can reverse the data if required. However, during a write operation the contents of the memory are read and compared to the input data and if different the new input data is written. If the new data is the same rewriting is inhibited. If may also be desirable to detect the data that may be marginal. Such data is the stored data that is the same as the input data but is near the end of its retention period. In this case rewriting or restoring the data is desired. It is important that the means of implementing this automatic restore feature operate over the full range of environmental conditions (such as temperature and radiation) to which the device may be subjected.
One such prior art method which has been utilized, requires the adding of a current to the circuit which detects the data in such a way that it opposes the states of the memory device. Two memory transistors per bit are used and are written to opposite states. One is shifted slightly positive, the other is slightly negative. Each transistor drives a node of a flip flop which is used to detect the data. If the difference between the two memory devices is above some minimum, the current they supply will overcome this added current, and stored data will be detected and the writing will be inhibited. If, however, the difference is below the minimum, the complement of the stored data will be detected and rewriting or restoring of the data will occur. This technique has been tried using computer simulation and can be made to work under a given set of conditions such as pre-radiation and room temperature. However, difficulty is encountered when the transistor parameters are changed to simulate the post radiation 125.degree. C. case. This occurs because the MOS FETS used to control the added current do not track the memory transistors with respect to temperature and radiation effects. The present circuit overcomes the prior art difficulties by providing an automatic data restore apparatus.